In a field effect transistor, the ability to engineer or shape the electric field at the drain edge of the gate is critical for reducing the device dynamic on-resistance and increasing the device breakdown voltage, which are two key parameters for high voltage GaN devices.
In the prior art, various approaches to modifying the electric field have been described. H. Xing, Y. Dora, A. Chini, S. Heikman, S. Keller, and U. k. Mishra, “High breakdown voltage AlGaN-GaN HEMTs Achieved by Multiple Field Plates,” IEEE Electron Dev. Lett., vol. 25, no. 4, April 2004describes multiple field plate devices to enhance the breakdown voltage. Flat field plates and combinations of flat field plates are also described in U.S. Pat. No. 7,573,078 B2, “Wide bandgap transistors with Multiple Field Plates” to Wu et al.
In the prior art, the use of a gate connected slanted field plate is described by Y. Pei, Z. Chen, D. Brown, S. Keller, S. P. Denbaars, and U. K. Mishra, “Deep-Submicrometer AlGaN/GaN HEMTs With Slant Field Plates”, IEEE Electron Dev. Lett., vol. 30, no. 4, April 2009. A paper by Y. Dora, A. Chakraborty, L. McCarthy, S. Keller, S. P. Denbaars, and U. K. Mishra, “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs with Integrated Slant Field Plates”, IEEE Electron Dev. Lett., vol. 27, no. 9, September 2006, also describes gate connected slant field plates to reduce the peak electric field for high voltage breakdown operation.
Slanted structures have advantages but are difficult to fabricate using traditional photolithography techniques, and have not been widely used. Further, a disadvantage of a gate connected field plate is higher device Miller capacitance and higher parasitic source resistance, both of which are undesirable.
What is needed is an improved field plate and method for fabricating an improved field plate. This is particularly needed for GaN-based transistors due to the unique difficulties of surface passivation and traps in the Group III-nitride materials, which can be exacerbated by a non-uniform electric field between the gate and drain. What would be desirable is to optimize the electric field between the gate and drain of the device to reduce the dynamic on-resistance and enhance the breakdown voltage, while lowering the device Miller capacitance and the parasitic source resistance. The embodiments of the present disclosure answer these and other needs.